This invention relates, in general, to static random access memories (SRAMs), and more particularly to SRAMs designed to be automatically generated by a computer.
A SRAM compiler is a computer program which can synthesize different memory configurations. Variables which determine a specific memory configuration are word width, number of words, and number of memory blocks. A SRAM compiler program creates a netlist of the memory, simulates the worst case delay path through the memory to generate timing information, builds a symbol of the SRAM for placement in a schematic, builds a simulation model with the timing information, creates a physical layout of the SRAM, builds a routing abstraction of the SRAM, and creates a power grid structure for the SRAM. In general, a SRAM compiler is used to generate memories for application specific integrated circuits (ASICs) such as a gate array or a standard cell circuit. A compiled SRAM may be one of many components which make up an integrated circuit.
A netlist of a SRAM is a schematic diagram of the SRAM stored on a computer. The netlist includes all elements which comprise the SRAM such as transistors, resistors, and capacitors as well as the interconnections between all the elements. The netlist can also be a hierarchical description having different levels, each level being a different description of the SRAM. For example, a first level could be a symbol of the SRAM with a corresponding table having timing parameters of the SRAM. A second level could be a block level schematic diagram of the SRAM. Each block of the block level schematic having its own table of timing parameters. A third level could be a transistor level schematic diagram of the SRAM. In general, the netlist is a description of the SRAM and is used for simulation and layout generation of the SRAM.
A SRAM generated by a compiler contrasts greatly with a SRAM designed for the general marketplace as a stand alone part. Typically, general product SRAMs are full custom designs which focus on memory density, speed, power, yield, and package size. All of these constraints must be met within a short design cycle time to introduce a successful SRAM in a highly competitive market. Due to the large size of these memories (256K bits and larger) block architecture's are used almost exclusively to meet SRAM target access speeds. The trend in full custom SRAM design is to build in limited configurability. Architecture's which allow variable word widths of the most common sizes are designed into the memory which decreases design cycle time. Also, large SRAMs are designed so they can be modified to a smaller configuration (for example 256K to 64K). This allows parts to be salvaged if yields are poor at the larger memory size or a faster version of the SRAM may be offered in the smaller configuration.
Creating the SRAM compiler is a task which involves both design and computer resources. Memory sizes and word widths on an ASIC can vary drastically depending on the customer application. Initial efforts attempted to take existing full custom memory designs and build them into memory compilers. Writing the computer code to create a configurable memory from a full custom design proved to be an extremely difficult task. Most abandoned this approach and created new memory designs which simplified writing the code to synthesize various memory configurations and reduce the complexity of building the physical layout of the SRAM.
Two features are typical of most SRAM compiler designs. First, the compiler builds a single block of memory for the application. Second, decoding stages are designed to minimize layout changes which reduces the complexity of the physical layout compiler. For large memory sizes both of these standard compiler attributes reduce SRAM performance. Larger memory array sizes increase loadings on outputs of decoder circuits and memory cells, decreasing SRAM access times. Building the decoding circuits to simplify layout changes often compromises performance for high row/column counts.
ASIC users are building complex integrated circuits using standard cell and gate array approaches. Large circuit blocks such as microprocessor core (a microprocessor circuit for use in an ASIC, typically stripped of its high drive outputs and other circuitry not essential for an embedded use within an ASIC), ROM, SRAM, multipliers, and register files are common elements used within an integrated circuit design. The user integrates these elements on a single integrated circuit (or multiple integrated circuits) to reduce component count and increase system speed. In general, large amounts of memory are required in complex integrated circuit designs. The memory required typically takes the form of a large single SRAM or multiple smaller SRAMs. The main limitation in a SRAM generated by a computer (compiled SRAM) is performance. The memory size is dictated by the largest SRAM that can be formed that meets the system speed requirements of an integrated circuit. Users expect performance levels similar to those of standard SRAM parts sold on the market. Presently, compilers have been unable to generate SRAMs approaching the speed/density of the full custom SRAM designs.
Accordingly, it would be desirable to provide an SRAM design having a structure that is easily generated for different configurations yet approaches speeds/densities of full custom SRAM designs.